The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2012

Filed:

Feb. 21, 2008
Applicants:

Yuichiro Mahara, Fujisawa, JP;

Akihiro Machida, Kyonan, JP;

Teruo Okamura, Yokohama, JP;

Sojiro Hagihara, Yokohama, JP;

Inventors:

Yuichiro Mahara, Fujisawa, JP;

Akihiro Machida, Kyonan, JP;

Teruo Okamura, Yokohama, JP;

Sojiro Hagihara, Yokohama, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A PDP apparatus having a driving circuit in which a circuit for applying a rising-slope waveform in a reset period, a circuit for applying a falling-slope waveform, and a clamp circuit for generating a falling waveform having a dulled waveform between the rising-slope waveform and the falling-slope waveform are comprised. The clamp circuit comprises a bidirectional switch having two FETs, and a gate feedback circuit is connected to a gate portion of the FET at a panel side. The PDP apparatus reduces a current noise occurring in a sustain electrode throughout the panel when switching the rising-slope waveform and the falling-slope waveform, thereby solving problems such as an increase of unnecessary radiation and stress on elements such as FETs on the path.


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