The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2012

Filed:

May. 21, 2010
Applicants:

Anthony L. Tsangaropoulos, San Carlos, CA (US);

David Francois Guillou, Pittsburgh, PA (US);

Inventors:

Anthony L. Tsangaropoulos, San Carlos, CA (US);

David Francois Guillou, Pittsburgh, PA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01); H03K 21/00 (2006.01); H03K 21/08 (2006.01); H03K 21/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fand outputs some integer fraction of those pulses at an instantaneous frequency fthat is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives an accumulator increment (i.e., the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to an overflow. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input from a pseudo-random noise generator.


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