The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2012

Filed:

Dec. 08, 2010
Applicants:

Masaru Koyanagi, Tokyo, JP;

Fumiyoshi Matsuoka, Kawawsaki, JP;

Yasuhiro Suematsu, Yokohama, JP;

Inventors:

Masaru Koyanagi, Tokyo, JP;

Fumiyoshi Matsuoka, Kawawsaki, JP;

Yasuhiro Suematsu, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A buffer circuit in accordance with an embodiment comprises output transistors connected between a first fixed voltage terminal and an output terminal, and gate control transistors connected between a second fixed voltage terminal and a gate of one of the output transistors or between two of gates of the output transistors. The output transistors are configured to turn on to change a voltage of the output terminal. The gate control transistors are configured to apply a gate voltage to the gates of the output transistors. A gate of each of the gate control transistors is applied with a certain voltage, such that when a source of each of the gate control transistors changes from a first potential to a second potential, a potential difference between the gate and the source attains a threshold voltage or greater, whereby each of the gate control transistors is turned on.


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