The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2012

Filed:

Dec. 10, 2010
Applicants:

Kazuo Nishi, Kouhu, JP;

Hiroki Adachi, Kai, JP;

Junya Maruyama, Ebina, JP;

Naoto Kusumoto, Isehara, JP;

Yuusuke Sugawara, Minamiarupusu, JP;

Tomoyuki Aoki, Isehara, JP;

Eiji Sugiyama, Atsugi, JP;

Hironobu Takahashi, Minamiarupusu, JP;

Inventors:

Kazuo Nishi, Kouhu, JP;

Hiroki Adachi, Kai, JP;

Junya Maruyama, Ebina, JP;

Naoto Kusumoto, Isehara, JP;

Yuusuke Sugawara, Minamiarupusu, JP;

Tomoyuki Aoki, Isehara, JP;

Eiji Sugiyama, Atsugi, JP;

Hironobu Takahashi, Minamiarupusu, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 31/0352 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a semiconductor device formed over an insulating substrate, typically a semiconductor device having a structure in which mounting strength to a wiring board can be increased in an optical sensor, a solar battery, or a circuit using a TFT, and which can make it mount on a wiring board with high density, and further a method for manufacturing the same. According to the present invention, in a semiconductor device, a semiconductor element is formed on an insulating substrate, a concave portion is formed on a side face of the semiconductor device, and a conductive film electrically connected to the semiconductor element is formed in the concave portion.


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