The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2012
Filed:
Jan. 19, 2010
Rouying Zhan, Gilbert, AZ (US);
Amaury Gendron, Scottsdale, AZ (US);
Chai Ean Gill, Chandler, AZ (US);
Rouying Zhan, Gilbert, AZ (US);
Amaury Gendron, Scottsdale, AZ (US);
Chai Ean Gill, Chandler, AZ (US);
Freescale Semiconductors, Inc., Austin, TX (US);
Abstract
A stacked electrostatic discharge (ESD) protection clamp (-) for protecting associated devices or circuits () comprises two or more series coupled (stacked) bipolar transistors () whose individual trigger voltages Vtdepend on their base-collector spacing D. A first (--) of the transistors () has a spacing Dchosen within a D range Zwhose slope (ΔVt/ΔD) has a first value (ΔVt/ΔD), and a second (--) of the transistors () has a spacing value Dchosen within a D range Zor Zwhose slope (ΔVt/ΔD) has a second value (ΔVt/ΔD)less than the first value (ΔVt/ΔD). The sensitivity of the ESD stack trigger voltage Vtto base-collector spacing variations ΔD during manufacture is much reduced, for example, by as much as 50% for a 2-stack and more for 3-stacks and beyond. A wide range of Vtvalues can be obtained that are less sensitive to unavoidable manufacturing spacing variations ΔD.