The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2012
Filed:
Jan. 12, 2011
Philippe Meunier-beillard, Kortenberg, BE;
Johannes Josephus Theodorus Marinus Donkers, Valkenswaard, NL;
Hans Mertens, Leuven, BE;
Tony Vanhoucke, Bierbeek, BE;
Philippe Meunier-Beillard, Kortenberg, BE;
Johannes Josephus Theodorus Marinus Donkers, Valkenswaard, NL;
Hans Mertens, Leuven, BE;
Tony Vanhoucke, Bierbeek, BE;
NXP B.V., Eindhoven, NL;
Abstract
Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer () and a sacrificial layer () on a mono-crystalline silicon substrate surface (); patterning the first stack to form a trench () extending to the substrate; depositing a silicon layer () over the resultant structure; depositing a silicon-germanium-carbon layer () over the resultant structure; selectively removing the silicon-germanium-carbon layer () from the sidewalls of the trench (); depositing a boron-doped silicon-germanium-carbon layer () over the resultant structure; depositing a further silicon-germanium-carbon layer () over the resultant structure; depositing a boron-doped further silicon layer () over the resultant structure; forming dielectric spacers () on the sidewalls of the trench (); filling the trench () with an emitter material (); exposing polysilicon regions () outside the side walls of the trench by selectively removing the sacrificial layer () of the first stack; implanting boron impurities into the exposed polysilicon regions () to define base implants; and exposing the resultant structure to a thermal budget for annealing the boron impurities. A HBT formed by this method is also disclosed.