The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2012

Filed:

Nov. 14, 2008
Applicants:

Yoshio Kawashima, Osaka, JP;

Takumi Mikawa, Shiga, JP;

Ryoko Miyanaga, Nara, JP;

Takeshi Takagi, Kyoto, JP;

Inventors:

Yoshio Kawashima, Osaka, JP;

Takumi Mikawa, Shiga, JP;

Ryoko Miyanaga, Nara, JP;

Takeshi Takagi, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A nonvolatile memory device includes via holes () formed at cross sections where first wires () cross second wires (), respectively, and current control elements () each including a current control layer (), a first electrode layer () and a second electrode layer () such that the current control layer () is sandwiched between the first electrode layer () and the second electrode layer (), in which resistance variable elements () are provided inside the via holes (), respectively, the first electrode layer () is disposed so as to cover the via hole (), the current control layer () is disposed so as to cover the first electrode layer (), the second electrode layer () is disposed on the current control layer (), a wire layer () of the second wire is disposed on the second electrode layer (), and the second wires () each includes the current control layer (), the second electrode layer () and the wire layer () of the second wire.


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