The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8239708 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 07, 2012

Filed:

May. 29, 2009
Applicants:

Jin-kwon Park, Suwon-si, KR;

Cheon-su Lee, Seoul, KR;

Jae-shin Lee, Seoul, KR;

Min-joung Lee, Suwon-si, KR;

Inventors:

Jin-kwon Park, Suwon-si, KR;

Cheon-su Lee, Seoul, KR;

Jae-shin Lee, Seoul, KR;

Min-Joung Lee, Suwon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.


Find Patent Forward Citations

Quick Actions:

Park, Jin-kwon. (2012). System on chip (soc) device verification system using memory interface (U.S. Patent No. 8239708). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8239708

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…