The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2012

Filed:

Dec. 29, 2008
Applicants:

Luca Magagni, Bologna, IT;

Luca Ciccarelli, Rimini, IT;

Alberto Fazzi, Eindhoven, NL;

Roberto Canegallo, Rimini, IT;

Roberto Guerrieri, Bologna, IT;

Inventors:

Luca Magagni, Bologna, IT;

Luca Ciccarelli, Rimini, IT;

Alberto Fazzi, Eindhoven, NL;

Roberto Canegallo, Rimini, IT;

Roberto Guerrieri, Bologna, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, unknown;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A communication system includes first and second independently clocked devices, comprising, for each device, a transmitter and a receiver connected to each other in a crossed way in correspondence of an inter-chip communication channel. The communication system further comprises a synchronizer in turn including at least a first and a second synchronization block, having respective input terminals connected to the receivers and respective output terminals connected to the transmitters and comprising at least: a test pattern generator that generates a programmable test pattern signal; a pattern detector to check a matching between stored and received test pattern signals and thus lock corresponding clock phases of the synchronization blocks in case of positive result of this check; and a delay block able to change the clock phases until a synchronized condition of the synchronization blocks is verified, this synchronized condition corresponding to a matching between stored and received test pattern signals.


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