Delay line calibration mechanism and related multi-clock signal generator

Abstract

A delay line calibration mechanism includes a first delay line, a second delay line, a phase detector, and a controller. The first delay line receives a first pulse and a first delay selection signal, and delays the first pulse for a first delay period according to the first delay selection signal to output a first delayed pulse. The second delay line receives a second pulse and a second delay selection signal, and delays the second pulse for a second delay period according to the second delay selection signal to output a second delayed pulse. The phase detector generates a phase difference signal indicating the phase difference between the first delayed pulse and the second delayed pulse by comparing the first delayed pulse and the second delayed pulse. The controller generates the second delay selection signal, and generates the first delay selection signal according to the phase difference signal.