The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2012
Filed:
Aug. 30, 2010
Toshio Yamada, Kawasaki, JP;
Kazuo Tanaka, Kawasaki, JP;
Akinobu Watanabe, Kawasaki, JP;
Shigeru Yamamoto, Kokubunji, JP;
Yukio Hiraiwa, Kokubunji, JP;
Toshio Yamada, Kawasaki, JP;
Kazuo Tanaka, Kawasaki, JP;
Akinobu Watanabe, Kawasaki, JP;
Shigeru Yamamoto, Kokubunji, JP;
Yukio Hiraiwa, Kokubunji, JP;
Renesas Electronics Corporation, kanagawa, JP;
Abstract
A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET ('control' MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.