The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2012
Filed:
Aug. 04, 2010
Shyam Ramji, Lagrangeville, NY (US);
Bella Dubrov, Tel-Aviv, IL;
Haggai Eran, Haifa, IL;
Ari Freund, Haifa, IL;
Edward F. Mark, Poughkeepsie, NY (US);
Timothy A. Schell, Poughkeepsie, NY (US);
Shyam Ramji, Lagrangeville, NY (US);
Bella Dubrov, Tel-Aviv, IL;
Haggai Eran, Haifa, IL;
Ari Freund, Haifa, IL;
Edward F. Mark, Poughkeepsie, NY (US);
Timothy A. Schell, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Assigning pins to macro-blocks of an Integrated Circuit (IC) chip is described. The macro-block pin assignments are automatically placed using Constraint Programming (CP) techniques to position the pins on the periphery of a macro-block. Bus-ordering and pin-spacing constraints are performed considering all the nets forming the IC design simultaneously. The CP formulation includes modeling detailed and discrete constraints required to achieve an optimal pin-assignment. A stochastic CSP solver is used to define the cost function on search points giving full assignments to all the variables. The macro-block pins are ultimately moved to computed locations.