The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2012
Filed:
Aug. 25, 2010
Benjiman L. Goodman, Cedar Park, TX (US);
Nathaniel D. Hieter, Hopewell Junction, NY (US);
Jeremy T. Hopkins, Round Rock, TX (US);
Samuel I. Ward, Austin, TX (US);
Benjiman L. Goodman, Cedar Park, TX (US);
Nathaniel D. Hieter, Hopewell Junction, NY (US);
Jeremy T. Hopkins, Round Rock, TX (US);
Samuel I. Ward, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.