Method and apparatus for ensuring data cache coherency

Abstract

An apparatus for controlling memory access in a multithreaded processor supporting a plurality of threads is provided. The apparatus includes a processor core; a cache memory storing data accessible by each of the plurality of threads; a main memory storing data accessible by a plurality of threads; an incoherency detection module; and a memory arbiter. The incoherency detection module is connected between the processor core and the memory arbiter, and the memory arbiter is connected between the incoherency detection module and the main memory. There is a separate request queue for each thread for read and write requests sent from the cache memory to the memory arbiter. The incoherency detection module stores an indication of a memory address for each write request sent from the cache memory to the main memory in a write address memory, and compares the address of each subsequent read request sent from the cache memory with indications in the write address memory. If the address of the subsequent read request matches an indication, the incoherency detection module inserts a barrier corresponding to the read request into the request queue of the thread to which the matching indication belongs. The memory arbiter prevents the read request from accessing the memory bus until the corresponding barrier has been received by the memory arbiter.