The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2012
Filed:
Jan. 13, 2005
Patrick Joseph Bohrer, Austin, TX (US);
Orran Yaakov Krieger, Newton, MA (US);
Ramakrishnan Rajamony, Austin, TX (US);
Michael Rosenfield, Ridgefield, CT (US);
Hazim Shafi, Austin, TX (US);
Balaram Sinharoy, Poughkeepsie, NY (US);
Robert Brett Tremaine, Stormville, NY (US);
Patrick Joseph Bohrer, Austin, TX (US);
Orran Yaakov Krieger, Newton, MA (US);
Ramakrishnan Rajamony, Austin, TX (US);
Michael Rosenfield, Ridgefield, CT (US);
Hazim Shafi, Austin, TX (US);
Balaram Sinharoy, Poughkeepsie, NY (US);
Robert Brett Tremaine, Stormville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.