The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8230381 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 24, 2012

Filed:

May. 04, 2010
Applicants:

Katsuyuki Itoh, Hadano, JP;

Hironori Iwamoto, Hadano, JP;

Inventors:

Katsuyuki Itoh, Hadano, JP;

Hironori Iwamoto, Hadano, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
Abstract

With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the conventional method is troublesome because it is necessary to correct relative positional information of cells after confirming a result of temporary layout. Therefore, it takes time to obtain a layout result. To avoid these problems, cells of a specific type specified from outside, or cells satisfying specific conditions, are extracted and arranged first or limited to a layout position by specifying a layout position, then arranging the remaining cells using a general layout algorithm.


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Itoh, Katsuyuki. (2012). Method for designing cell layout of semiconductor integrated circuit (U.S. Patent No. 8230381). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8230381

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