The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2012
Filed:
Sep. 02, 2010
Susumu Kobayashi, Kanagawa, JP;
Morihisa Hirata, Kanagawa, JP;
Mototsugu Okushima, Kanagawa, JP;
Tomohiro Kitayama, Kanagawa, JP;
Tetsuya Katou, Kanagawa, JP;
Susumu Kobayashi, Kanagawa, JP;
Morihisa Hirata, Kanagawa, JP;
Mototsugu Okushima, Kanagawa, JP;
Tomohiro Kitayama, Kanagawa, JP;
Tetsuya Katou, Kanagawa, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
An ESD analysis method and computer program product are disclosed. A circuit simulation is executed of design data of a semiconductor integrated circuit including a first power supply pad, a second power supply pad and a plurality of current paths between the first power supply pad and the second power supply pad, to calculate potentials in the plurality of current paths, when one of an ESD current and an ESD voltage is applied between the first power supply pad and the second power supply pad. An ESD tolerance is checked by calculating a potential difference between a first node coupled to the first power supply pad and a second node coupled to the second power supply pad, based on the calculated potentials. The first node and the second node are determined as nodes to be coupled to a border cell upon the potential difference being lower than a predetermined value.