The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2012

Filed:

Oct. 18, 2010
Applicants:

Gang-feng Fang, Fremont, CA (US);

Wingyu Leung, Cupertino, CA (US);

Inventors:

Gang-Feng Fang, Fremont, CA (US);

Wingyu Leung, Cupertino, CA (US);

Assignee:

Chip Memory Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 29/788 (2006.01); H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method of an electrically programmable and erasable non-volatile memory cell fabricated using a single-poly, logic process with the addition of ONO deposition and etching is disclosed. In one embodiment, a non-volatile memory system includes at least one non-volatile memory cell consists of a SONOS transistor fabricated on a P substrate, with a deep N-well located in the P substrate, with a P-well located in the deep N-well. The memory cell further includes an access NMOS transistor, coupled to the SONOS transistor and located in the same P-well that includes an oxide only gate-dielectric. The cell can be fabricated in a modified logic process with other transistors and with their physical characteristics preserved.


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