Memory cell and an associated memory device

Abstract

A memory cell includes a pair of sub-cells, each including an access transistor, a storage transistor, and an isolation transistor that are serially coupled in sequence with their source/drain connected. The isolation transistor is shared with a sub-cell of an adjacent memory cell and always turned off, wherein the storage transistor is always turned on. A wordline is coupled to a gate of the access transistor of each sub-cell, and complementary bit lines are respectively coupled to sources/drains of the access transistors of the pair of sub-cells, such that data bit may be accessed between the bit line and the corresponding storage transistor through the corresponding access transistor.