The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2012

Filed:

Mar. 18, 2010
Applicants:

Tomoko Hara, Chino, JP;

Yoshihiko Nimura, Suwa, JP;

Inventors:

Tomoko Hara, Chino, JP;

Yoshihiko Nimura, Suwa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

An input-output interface circuit of the present invention includes an input-output terminal, an input buffer, a first MOS transistor of a first conductivity type formed in a floating well region, an output buffer for outputting a signal externally through the input-output terminal, an electrostatic protection circuit, and a floating well potential adjusting circuit, wherein the electrostatic protection circuit has a first resistance, and a diode connected between another end of the first resistance and a high level power supply potential, and the floating well potential adjusting circuit has a second resistance having one end connected to the input-output terminal, and a second MOS transistor of the first conductivity type having one end connected to another end of the second resistance, another end connected to the floating well region, and a gate connected to the high level power supply potential.


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