The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8228452 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 24, 2012

Filed:

Dec. 03, 2009
Applicants:

Jung-hee Lee, Suwon, KR;

Yoon-sung Um, Yongin, KR;

Jong-ho Son, Seoul, KR;

Jae-jin Lyu, Kyungki-do, KR;

Inventors:

Jung-Hee Lee, Suwon, KR;

Yoon-Sung Um, Yongin, KR;

Jong-Ho Son, Seoul, KR;

Jae-Jin Lyu, Kyungki-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
Abstract

A thin film transistor array panel is provided, which includes: an insulating substrate; a gate line formed on the substrate and including a gate electrode; a gate insulating layer formed on the gate line; a semiconductor layer formed on the gate insulating layer opposite the gate electrode; a data line formed on the gate insulating layer and including a first source electrode located on the semiconductor layer; first and second drain electrodes formed on the semiconductor layer, separated from each other and overlapping the gate electrode; a passivation layer formed on the data line and the first and second drain electrodes; and first and second pixel electrodes electrically connected to the first and second electrodes, respectively, wherein an overlapping area between the gate electrode and the first drain electrode is different from an overlapping area between the gate electrode and the second drain electrode.


Find Patent Forward Citations

Lee, Jung-Hee. (2012). Liquid crystal display and thin film transistor array panel therefor (U.S. Patent No. 8228452). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8228452

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…