The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2012
Filed:
Mar. 03, 2010
Tien Duc Pham, San Jose, CA (US);
Sergey Shumarayev, Los Altos Hills, CA (US);
Richard G. Cliff, Los Altos, CA (US);
Tim Tri Hoang, San Jose, CA (US);
Weiqi Ding, Fremont, CA (US);
Sriram Narayan, Pleasanton, CA (US);
Thungoc M. Tran, San Jose, CA (US);
Kumara Tharmalingam, San Jose, CA (US);
Tien Duc Pham, San Jose, CA (US);
Sergey Shumarayev, Los Altos Hills, CA (US);
Richard G. Cliff, Los Altos, CA (US);
Tim Tri Hoang, San Jose, CA (US);
Weiqi Ding, Fremont, CA (US);
Sriram Narayan, Pleasanton, CA (US);
Thungoc M. Tran, San Jose, CA (US);
Kumara Tharmalingam, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.