The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2012
Filed:
Jan. 30, 2009
Steven Huynh, Fremont, CA (US);
Matthew A. Grant, Palo Alto, CA (US);
Gary M. Hurtz, Pleasanton, CA (US);
David J. Kunst, Cupertino, CA (US);
Trey A. Roessig, Palo Alto, CA (US);
Steven Huynh, Fremont, CA (US);
Matthew A. Grant, Palo Alto, CA (US);
Gary M. Hurtz, Pleasanton, CA (US);
David J. Kunst, Cupertino, CA (US);
Trey A. Roessig, Palo Alto, CA (US);
Active-Semi, Inc., , VG;
Abstract
A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.