Delay period analyzing apparatus, delay period analyzing method, and delay period analyzing program

Abstract

A apparatus for analyzing a delay in path between flip-flops, including: a calculator that performs delay calculation and generates a delay calculation result on wiring and layout of logic circuits; a analyzer that performs delay analysis for each delay calculation results, and generates delay analysis results for paths by adding delay of logic elements and flip-flops, and by multiplying the sum calculated by a scattering coefficient; a sorter that stores delay analysis results for paths, thereby generating a maximum delay sorting result; a probability calculator that generates probability density functions for paths on a condition by performing processing in which a path is selected from paths in order of maximum delay on the maximum delay sorting result, and a probability density function is generated for the path selected between the flip-flops; and a value calculator that performs maximum value calculation for the probability density functions for all the paths.