The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2012

Filed:

Dec. 16, 2008
Applicants:

Guy L. Guthrie, Austin, TX (US);

Alvan W. NG, Austin, TX (US);

Michael S. Siegel, Raleigh, NC (US);

William J. Starke, Round Rock, TX (US);

Derek E. Williams, Austin, TX (US);

Phillip G. Williams, Leander, TX (US);

Inventors:

Guy L. Guthrie, Austin, TX (US);

Alvan W. Ng, Austin, TX (US);

Michael S. Siegel, Raleigh, NC (US);

William J. Starke, Round Rock, TX (US);

Derek E. Williams, Austin, TX (US);

Phillip G. Williams, Leander, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A data processing system includes a first processing unit and a second processing unit coupled by an interconnect fabric. The first processing unit has a first processor core and associated first upper and first lower level caches, and the second processing unit has a second processor core and associated second upper and lower level caches. In response to a data request, a victim cache line is selected for castout from the first lower level cache. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.


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