The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2012
Filed:
Aug. 11, 2009
Applicants:
Bharadwaj Amrutur, Bangalore, IN;
Bishnu Prasad Das, Khurda, IN;
Inventors:
Bharadwaj Amrutur, Bangalore, IN;
Bishnu Prasad Das, Khurda, IN;
Assignee:
Indian Institute of Science, Bangalore, IN;
Primary Examiner:
Int. Cl.
CPC ...
G01R 29/00 (2006.01); G06F 11/26 (2006.01);
U.S. Cl.
CPC ...
Abstract
A system and method to measure a delay of an individual logic gate in an unmodified form on a chip using a digitally reconfigurable ring oscillator (RO) that is on the chip is provided. A system of linear equations is established for different configuration settings of the ring oscillator and solved to determine a delay of an individual gate.
Amrutur, Bharadwaj. (2012). Gate delay measurement circuit and method of determining a delay of a logic gate (U.S. Patent No. 8224604). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8224604
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile