The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2012
Filed:
Dec. 22, 2009
Sangeeta Raman, San Jose, CA (US);
Tim Tri Hoang, San Jose, CA (US);
Sergey Yuryevich Shumarayev, Los Altos Hills, CA (US);
Sangeeta Raman, San Jose, CA (US);
Tim Tri Hoang, San Jose, CA (US);
Sergey Yuryevich Shumarayev, Los Altos Hills, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Equalizer circuitry on an integrated circuit ('IC') includes a plurality of NMOS equalizer stages connected in series. Each NMOS stage may include folded active inductor circuitry. Each NMOS stage may also include various circuit elements having controllably variable circuit parameters so that the equalizer can be controllably adapted to perform for any of a wide range of high-speed serial data signal bit rates and other variations of communication protocols and/or communication conditions. For example, each NMOS stage may be programmable to control at least one of bandwidth and power consumption of the equalizer circuitry. The equalizer may also have a first PMOS stage that can be used instead of the first NMOS stage in cases in which the voltage of the incoming signal to be equalized is too low for an initial NMOS stage.