The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2012
Filed:
Jan. 28, 2011
Christian Grewing, Stockholm, SE;
Anders Jakobsson, Stockholm, SE;
Ola Pettersson, Stockholm, SE;
Anders Emericks, Stockholm, SE;
Bingxin LI, Stockholm, SE;
Christian Grewing, Stockholm, SE;
Anders Jakobsson, Stockholm, SE;
Ola Pettersson, Stockholm, SE;
Anders Emericks, Stockholm, SE;
Bingxin Li, Stockholm, SE;
Huawei Technologies Co., Ltd., Shenzhen, CN;
Abstract
A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) () comprising a voltage controlled oscillator (VCO) () controlled by means of a tuning voltage (V) is disclosed. An embodiment of the invention compares the VCO tuning voltage (V) to a low threshold voltage (V) and a high threshold voltage (V), creating an oscillation of the VCO tuning voltage by offsetting the divider value such that the PLL () forces the tuning voltage (V) towards the high threshold voltage (V) when the low threshold voltage (V) is reached, and offsetting the divider value such that said PLL () forces the tuning voltage (V) towards the low threshold voltage (V) when the high threshold voltage (V) is reached, measuring the period of the oscillation between the high and the low threshold voltage of the VCO tuning voltage by counting the number of cycles of a reference clock signal (clk), and comparing the number of reference clock cycles to a reference number of clock cycles to determine the relative loop bandwidth of the PLL ().