The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2012
Filed:
Jul. 16, 2009
Dilip Sangam, Saratoga, CA (US);
Hendrik Santo, San Jose, CA (US);
Sean Chen, Sunnyvale, CA (US);
Minjong Kim, San Jose, CA (US);
Sivaprakash Kannan, Santa Clara, CA (US);
Balaji Virajpet, San Jose, CA (US);
Dilip Sangam, Saratoga, CA (US);
Hendrik Santo, San Jose, CA (US);
Sean Chen, Sunnyvale, CA (US);
Minjong Kim, San Jose, CA (US);
Sivaprakash Kannan, Santa Clara, CA (US);
Balaji Virajpet, San Jose, CA (US);
Atmel Corporation, San Jose, CA (US);
Abstract
The innovation relates to systems and/or methodologies for error detection during sub-assembly in high voltage analog circuits. A signal driver communicates test signals to one or more high voltage analog circuits, and a state machine compares the electrical and/or thermal responses of the high voltage analog circuits to a set of predetermined expected results (e.g., signatures). The signal driver and state machine can be incorporated into the high voltage analog circuits. The expected results can be stored in the target circuits in the form of look-up tables, matrices, and so forth. Errors, such as, dry solders and bridge solders can be determined based on the comparison of the obtained responses to the expected signatures.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile