The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2012

Filed:

Apr. 17, 2009
Applicants:

John M Cohn, Richmond, VT (US);

James A. Culp, Downington, PA (US);

Ulrich A. Finkler, Mahopac, NY (US);

Fook-luen Heng, Yorktown Heights, NY (US);

Mark A. Lavin, Katonah, NY (US);

Jin Fuw Lee, Yorktown Heights, NY (US);

Lars W. Liebmann, Poughquag, NY (US);

Gregory A. Northrop, Putnam Valley, NY (US);

Nakgeuon Seong, Wappingers Falls, NY (US);

Rama N. Singh, Bethel, CT (US);

Leon Stok, Croton on Hudson, NY (US);

Pieter J. Woeltgens, Yorktown Heights, NY (US);

Inventors:

John M Cohn, Richmond, VT (US);

James A. Culp, Downington, PA (US);

Ulrich A. Finkler, Mahopac, NY (US);

Fook-Luen Heng, Yorktown Heights, NY (US);

Mark A. Lavin, Katonah, NY (US);

Jin Fuw Lee, Yorktown Heights, NY (US);

Lars W. Liebmann, Poughquag, NY (US);

Gregory A. Northrop, Putnam Valley, NY (US);

Nakgeuon Seong, Wappingers Falls, NY (US);

Rama N. Singh, Bethel, CT (US);

Leon Stok, Croton on Hudson, NY (US);

Pieter J. Woeltgens, Yorktown Heights, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 19/00 (2011.01); G03F 1/00 (2012.01); G21K 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.


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