The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2012
Filed:
Mar. 04, 2009
Robert P. Masleid, Monte Sereno, CA (US);
James Ballard, Palo Alto, CA (US);
Robert P. Masleid, Monte Sereno, CA (US);
James Ballard, Palo Alto, CA (US);
Oracle America, Redwood Shores, CA (US);
Abstract
A semiconductor die includes: a clock distribution network that distributes a clock signal within the die. The clock distribution network includes: a clock tree corresponding to one or more metal layers of the die, a plurality of clock spines corresponding to a metal layer of the die, a plurality of clock wings corresponding to a metal layer of the die, a plurality of clock grid drivers placed in one or more gaps of a floorplan corresponding to the semiconductor layer of the die, a clock grid placed in the one or more gaps of the floorplan, a plurality of buffers placed in a local gain buffer pair configuration wherein the local gain buffer pair connects the clock grid to a shorting bar, and a plurality of conductors that connect the shorting bar to a plurality of loads.