The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2012

Filed:

Oct. 21, 2005
Applicants:

Gottfried Ungerboeck, Langnau a.A., CH;

Scott Richard Powell, Carlsbad, CA (US);

Ba-zhong Shen, Irvine, CA (US);

Inventors:

Gottfried Ungerboeck, Langnau a.A., CH;

Scott Richard Powell, Carlsbad, CA (US);

Ba-Zhong Shen, Irvine, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/12 (2006.01); H04L 9/16 (2006.01); H04L 9/24 (2006.01); G06F 7/58 (2006.01); G06F 1/02 (2006.01); H04L 9/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

A two-stage block synchronization and scrambling module includes a synchronization PRNG module, a scramble PRNG module, a summing module, and a storage module. The synchronization PRNG module is clocked once per N+1 bit PCS frame (N arbitrary) to produce a synchronization bit and a pseudo-random starting state for the scramble PRNG. The scramble PRNG module is clocked N times per PCS frame to produce a cipher stream starting with a pseudo-random state from the synchronization PRNG. The summing module is operably coupled to sum the cipher stream and a PCS frame payload to produce scrambled payload. The storage module is operably coupled to store the scrambled payload with the synchronization bit. Synchronization bits from successive frames are a running bit-serial representation of the synchronization PRNG state and are used by the receiver to synchronize with the transmit scrambler.


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