Methods and apparatuses for clock domain crossing

Abstract

Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The time delay ensures proper setup and hold time parameters for the second clock domain relative to the first clock domain. A differentiator generates output information in the second clock domain by delaying the second domain accumulation and subtracting the delayed second domain accumulation from the second domain accumulation. The systems and methods preserve temporal characteristics of the input information in the first clock domain when it is transferred to the second clock domain as the output information.