The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2012
Filed:
Jun. 13, 2011
Chua-chin Wang, Kaohsiung, TW;
Wei-chih Chang, Kaohsiung, TW;
Tzung-je Lee, Kaohsiung, TW;
Kuo-chan Huang, Tainan, TW;
Chua-Chin Wang, Kaohsiung, TW;
Wei-Chih Chang, Kaohsiung, TW;
Tzung-Je Lee, Kaohsiung, TW;
Kuo-Chan Huang, Tainan, TW;
Himax Technologies Limited, , TW;
Abstract
A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.