The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2012
Filed:
Oct. 05, 2009
Hiroyuki Mori, Kyoto, JP;
Kazushige Kawasaki, Kyoto, JP;
Hiroyuki Mori, Kyoto, JP;
Kazushige Kawasaki, Kyoto, JP;
International Business Machines Corporation, Armonk, NY (US);
Abstract
Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a coreless substrate which includes: a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter φis about 95 μm and a contact portion whose diameter φc is about 75 μm. The main surface of the contact portion is exposed at the main surface of the dielectric layer. Since diameter φc of the contact portion is substantially the same as diameter φof an under bump metal at the semiconductor chip side, even if mechanical stress is applied in a direction in which the semiconductor chip is peeled off from the coreless substrate, the stress disperses evenly to both of the connecting pad and the under bump metal, and thus rupture is less prone to occur.