The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2012
Filed:
Sep. 11, 2009
Yasuhiro Agata, Osaka, JP;
Noriaki Narumi, Osaka, JP;
Yoshinobu Yamagami, Osaka, JP;
Akira Masuo, Hyogo, JP;
Yasuhiro Agata, Osaka, JP;
Noriaki Narumi, Osaka, JP;
Yoshinobu Yamagami, Osaka, JP;
Akira Masuo, Hyogo, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A system LSI () having a logic circuit () and a plurality of SRAM macros () includes a power supply circuit () configured to receive a voltage (VDDP) supplied from the outside of the system LSI (), and to generate a stabilized voltage (VDDM) lower than the voltage (VDDP). An SRAM memory cell () of each of the plurality of SRAM macros () is supplied with the voltage (VDDM) generated by the power supply circuit (), and an SRAM logic circuit () of each of the plurality of SRAM macros () is supplied with a voltage (VDD) supplied from the outside. In addition, the logic circuit () is supplied with the voltage (VDD) from the outside.
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