The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2012

Filed:

Aug. 25, 2010
Applicant:

Susumu Fujimura, Yokohama, JP;

Inventor:

Susumu Fujimura, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device, in which flag data read of a flag data region is performed during data write, comprises: a nonvolatile memory cell array having an ordinary data region and the flag data region allocated to a one page range in which read and write are simultaneously performed; and a one page amount of sense amplifiers, each of the sense amplifiers comprising a data latch for retaining write data. During read of the flag data by the sense amplifier circuit, in the case of one of the sense amplifiers corresponding to the flag data region, read flag data is transferred to the data latch. In the case of one of the sense amplifiers corresponding to the ordinary data region, write data retained by the data latch is rewritten regardless of read cell data.


Find Patent Forward Citations

Fujimura, Susumu. (2012). Semiconductor memory device and method of operating the same (U.S. Patent No. 8208309). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8208309

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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