The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2012

Filed:

Aug. 16, 2011
Applicants:

Patrick Sullivan, San Diego, CA (US);

Steven R. Bristow, San Jose, CA (US);

William R. Creek, San Diego, CA (US);

Jeffrey Allen King, San Francisco, CA (US);

Inventors:

Patrick Sullivan, San Diego, CA (US);

Steven R. Bristow, San Jose, CA (US);

William R. Creek, San Diego, CA (US);

Jeffrey Allen King, San Francisco, CA (US);

Assignee:

Intersil Americas Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/156 (2006.01); G01R 31/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A tester includes a device under test (DUT) power supply (DPS) with and input and output includes an amplifier configured to set an output voltage of the DPS output equal to an input voltage for the DPS. The DPS has a first output stage coupled to the amplifier and configured to source and sink current at the output of the DPS between a first voltage rail and a third voltage rail. The DPS has a second output stage coupled to the amplifier and configured to source and sink current to the output of the DPS between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.


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