The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 19, 2012

Filed:

Dec. 10, 2009
Applicants:

Lee Han Meng Eugene Lee, Muar, MY;

Kuan Yee Woo, Tampin, MY;

Inventors:

Lee Han Meng Eugene Lee, Muar, MY;

Kuan Yee Woo, Tampin, MY;

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor chip package having multiple leadframes is disclosed. Packages can include a first leadframe having a first plurality of electrical leads and a die attach pad having a plurality of tie bars, a second leadframe generally parallel to the first leadframe and having a second plurality of electrical leads, and a mold or encapsulant. Tie bars can be located on three main sides of the die attach pad, but not the fourth main side. Gaps in the first and second plurality of electrical leads can be enlarged or aligned with each other to enable the elimination of mold flash outside the encapsulated region, which can be accomplished with mold cavity bar protrusions. Additional components can include a primary die, a secondary die, an inductor and/or a capacitor. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes.


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