The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2012
Filed:
Jan. 12, 2010
Chun-ming Huang, Hsinchu, TW;
Chien-ming Wu, Hsinchu, TW;
Chih-chyau Yang, Hsinchu, TW;
Shih-lun Chen, Hsinchu, TW;
Chin-long Wey, Hsinchu, TW;
Chi-shi Chen, Hsinchu, TW;
Chi-sheng Lin, Hsinchu, TW;
Chun-Ming Huang, Hsinchu, TW;
Chien-Ming Wu, Hsinchu, TW;
Chih-Chyau Yang, Hsinchu, TW;
Shih-Lun Chen, Hsinchu, TW;
Chin-Long Wey, Hsinchu, TW;
Chi-Shi Chen, Hsinchu, TW;
Chi-Sheng Lin, Hsinchu, TW;
National Chip Implementation Center, Hsinchu, TW;
National Applied Research Laboratories, Hsinchu, TW;
Abstract
A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.