The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2012
Filed:
Jan. 26, 2010
Daisuke Ikeno, Yokohama, JP;
Tomonori Aoyama, Yokohama, JP;
Kazuaki Nakajima, Tokyo, JP;
Seiji Inumiya, Carmel, NY (US);
Takashi Shimizu, Yokohama, JP;
Takuya Kobayashi, Yokohama, JP;
Daisuke Ikeno, Yokohama, JP;
Tomonori Aoyama, Yokohama, JP;
Kazuaki Nakajima, Tokyo, JP;
Seiji Inumiya, Carmel, NY (US);
Takashi Shimizu, Yokohama, JP;
Takuya Kobayashi, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor device according to an embodiment of the present invention includes an N-type transistor formed in a first region on a substrate, and a P-type transistor formed in a second region on the substrate. The device includes the substrate, a first gate insulation film formed on the substrate in the first and second regions, and containing silicon, a second gate insulation film formed on the first gate insulation film in the first region, and containing first metal and oxygen, a third gate insulation film formed on the first gate insulation film in the second region, and containing second metal different from the first metal and oxygen, a fourth gate insulation film formed on the second and third gate insulation films in the first and second regions, and containing hafnium, and a gate electrode layer formed on the fourth gate insulation film in the first and second regions, and containing metal and nitrogen, a thickness of the gate electrode layer formed in the second region being greater than a thickness of the gate electrode layer formed in the first region.