The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2012
Filed:
Mar. 31, 2010
Hasan Arslan, Sunnyvale, CA (US);
Vinay Verma, Fremont, CA (US);
Sandor Kalman, Santa Clara, CA (US);
Hasan Arslan, Sunnyvale, CA (US);
Vinay Verma, Fremont, CA (US);
Sandor Kalman, Santa Clara, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
In one embodiment of the invention, a processor-implemented method is provided for routing of a partially routed circuit design. Modified signals of the partially routed circuit design are determined. A first set of routing constraints are applied by the processor to the unmodified signals of the circuit design. For each logic block of the circuit design, the number of the modified signals and the number of the unmodified signals connected to the logic block are determined. In response to one of the logic blocks having a ratio of the number of modified signals to the number of unmodified signals greater than a threshold ratio, the routing constraints are removed by the processor from one or more of the unmodified signals of the one of the logic blocks. The partially routed circuit design is then routed by the processor according to the remaining routing constraints, and the resulting netlist is stored.