The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2012
Filed:
Dec. 16, 2009
Philippe Garrault, Saint Andre le Gaz, FR;
Jennifer D. Baldwin, Boulder, CO (US);
Richard J. Leblanc, Longmont, CO (US);
Premduth Vidyanandan, Denver, CO (US);
Kenneth J. Stickney, Jr., Boulder, CO (US);
Carrie L. Kisiday, Fort Collins, CO (US);
Philippe Garrault, Saint Andre le Gaz, FR;
Jennifer D. Baldwin, Boulder, CO (US);
Richard J. LeBlanc, Longmont, CO (US);
Premduth Vidyanandan, Denver, CO (US);
Kenneth J. Stickney, Jr., Boulder, CO (US);
Carrie L. Kisiday, Fort Collins, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A process is provided for creating an input/output (I/O) model. A set of logical I/O pins of an unplaced and unrouted circuit design is determined. Pin placement is determined for one or more of the logical I/O pins on device pins of a target device. An I/O pin profile for each of the logical I/O pins is determined. A plurality of I/O pin models available on the target device are input and an I/O pin model is selected from the plurality of I/O pin models for each of the logical I/O pins according to the respective I/O pin profiles. An I/O model is generated including each selected I/O pin model within the I/O model. The generated I/O model is stored in a processor readable storage medium.