The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8193957 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 05, 2012

Filed:

Sep. 10, 2010
Applicant:

Masato Yoshioka, Kawasaki, JP;

Inventor:

Masato Yoshioka, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A successive approximation register analog-to-digital converter includes: a digital-to-analog converter that generates an analog voltage based on a digital code; a comparator that receives the analog voltage; a control circuit that generates a digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on a comparison result of the comparator; a delay circuit that resets the comparator based on a signal transition generated by delaying the comparison result; and an adjustment circuit that counts a value indicating a number of the signal transition being generated during a cycle of the external clock signal and adjusts a delay of the delay circuit according to a counted value.


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Yoshioka, Masato. (2012). Successive approximation register analog to digital converter (adc) and method of adjusting delay thereof (U.S. Patent No. 8193957). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8193957

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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