The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2012

Filed:

Oct. 04, 2007
Applicants:

Vrashank Gurudatta Shukla, Bangalore, IN;

James Garrett Homack, Dallas, TX (US);

John Eric Kunz, Dallas, TX (US);

Inventors:

Vrashank Gurudatta Shukla, Bangalore, IN;

James Garrett Homack, Dallas, TX (US);

John Eric Kunz, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

An aspect of the present invention validates ESD compliance by examining netlist data generated from a schematic level design of an integrated circuit. Routing and placement may be performed only after confirming that whether each protected circuit (having exposure to ESD current, without the protection circuit) is protected by an appropriate protection circuit. As a result, the design cycle time may be reduced. According to another aspect of the present invention, layout guidelines for each protection circuit is also considered in performing the routing and placement. As a result, the number of iterations in a design cycle may be reduced.


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