The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2012

Filed:

Dec. 22, 2008
Applicant:

Kouichi Yamada, Gifu, JP;

Inventor:

Kouichi Yamada, Gifu, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

A floating gate made of polysilicon is provided on a semiconductor substrate through the medium of a gate insulator. A side-wall insulating film is provided on each side wall of the floating gate. A first impurity diffusion layer, which occupies a space within the semiconductor substrate, is provided separately apart from the floating gate by a predetermined distance. A second impurity diffusion layer, which occupies a space within the semiconductor substrate, overlaps with the floating gate. Electrons are injected into the floating gate by applying a high voltage to the second impurity diffusion layer in capacitive coupling with the floating gate.


Find Patent Forward Citations

Yamada, Kouichi. (2012). Nonvolatile semiconductor memory device, method for manufacturing the same, and nonvolatile memory array (U.S. Patent No. 8189385). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8189385

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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