The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2012
Filed:
Jul. 19, 2010
Dan Zhu, High Point, NC (US);
Reuben Pascal Nelson, Colfax, NC (US);
Timir Raithatha, Greensboro, NC (US);
Wyn Palmer, Greensboro, NC (US);
John Cavey, Oak Ridge, NC (US);
Ziwei Zheng, Greensboro, NC (US);
Dan Zhu, High Point, NC (US);
Reuben Pascal Nelson, Colfax, NC (US);
Timir Raithatha, Greensboro, NC (US);
Wyn Palmer, Greensboro, NC (US);
John Cavey, Oak Ridge, NC (US);
Ziwei Zheng, Greensboro, NC (US);
Analog Devices, Inc., Norwood, MA (US);
Abstract
A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for storing the difference signal over time. The SDM may have a control input coupled to the buffer. The adder may have inputs coupled to the SDM and a source of an integer control word. The first frequency divider may have an input for receiving an external clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the external clock signal divided by (N+F/M).