The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2012

Filed:

Dec. 13, 2009
Applicants:

Makoto Saen, Kodaira, JP;

Kenichi Osada, Tokyo, JP;

Masanao Yamaoka, Kodaira, JP;

Tomonori Sekiguchi, Tama, JP;

Inventors:

Makoto Saen, Kodaira, JP;

Kenichi Osada, Tokyo, JP;

Masanao Yamaoka, Kodaira, JP;

Tomonori Sekiguchi, Tama, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 7/00 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TRT), and a circuit for executing a plurality of receptions (TRR, TRR, TRR) are connected to one penetration-electrode group (for example, TSVGL). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.


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