The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2012
Filed:
Jun. 25, 2010
Young Jean Song, Gyunggi-do, KR;
Shinichi Iizuka, Gyunggi-do, KR;
Youn Suk Kim, Gyunggi-do, KR;
Hyo Kun Bae, Seoul, KR;
Sang Hee Kim, Gyunggi-do, KR;
Jun Goo Won, Gyunggi-do, KR;
Joong Jin Nam, Seoul, KR;
Ki Joong Kim, Gyunggi-do, KR;
Jae Hyouck Choi, Gyunggi-do, KR;
Young Jean Song, Gyunggi-do, KR;
Shinichi Iizuka, Gyunggi-do, KR;
Youn Suk Kim, Gyunggi-do, KR;
Hyo Kun Bae, Seoul, KR;
Sang Hee Kim, Gyunggi-do, KR;
Jun Goo Won, Gyunggi-do, KR;
Joong Jin Nam, Seoul, KR;
Ki Joong Kim, Gyunggi-do, KR;
Jae Hyouck Choi, Gyunggi-do, KR;
Samsung Electro-Mechanics Co., Ltd., Gyunggi-do, KR;
Abstract
A power amplifier includes an inverter amplification section configured to amplify AC components and remove DC components from at least one input signal, an impedance matching section configured to match an impedance of a transmission path of the at least one input signal amplified by the inverter amplification section, and an amplification section configured to amplify an impedance-matched signal from the impedance matching section according to a predetermined gain. The inverter amplification section includes at least one P-channel metal-oxide semiconductor field effect transistor (MOS FET) having a gate configured to receive the at least one input signal and at least one N-channel MOS FET having a gate configured to receive the at least one input signal. The at least one P-channel MOS FET and the at least one N-channel MOS FET are serially connected.