The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 22, 2012

Filed:

Mar. 25, 2008
Applicant:

Torkel Arnborg, Stockholm, SE;

Inventor:

Torkel Arnborg, Stockholm, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 3/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electronic circuit comprises at least two transistors coupled in parallel, wherein the second transistor channel length is configured such that the threshold voltage of the second transistor is at a peak on a threshold voltage versus channel lengths curve arising from reverse short channel effects for a given semiconductor process. The first transistor is biased with a first gate-source voltage and a first drain-source voltage. The second transistor is biased with a second gate-source voltage and a second drain-source voltage. The first and second gate-source voltages are offset from each other by a gate-source voltage offset. The first and second drain-source voltages are offset from each other by a drain-source voltage offset. These bias conditions result in the transistors operating in different regions so that the second and third-order nonlinearities of the transistors substantially cancel each other out simultaneously.


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